The present invention relates to nonvolatile semiconductor memory devices. More particularly, the present invention relates to a low-cost nonvolatile semiconductor memory device capable of being embedded in LSI in a leading-edge standard CMOS process.
In recent years, there has been an increasing demand for incorporating secure information such as an encryption key for contents in system LSI in a leading-edge standard CMOS process. For this incorporation, the use of metal fuses has been considered. However, there is apprehension that information leakage might be caused by analysis. To prevent the leakage, inclusion of a nonvolatile semiconductor memory device capable of being rewritten at low cost is expected.
To mount a nonvolatile semiconductor memory device such as a flash memory on system LSI, a dedicated process is additionally needed in a standard CMOS process, so that the process cost increases and no leading-edge process can be used. In view of this, a low-cost nonvolatile semiconductor memory device capable of being embedded in LSI in a leading-edge standard CMOS process is needed.
To meet the need described above, a CMOS nonvolatile memory in which the respective gates of one NMOS and two PMOSs capable of being embedded in LSI in a leading-edge standard CMOS process together form a floating gate, the diffusion region of a first PMOS is used as a control gate during write operation and read operation and the diffusion region of a second PMOS is used during erase operation is known (see, Richard J. McPartland, et al., “1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications”, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161).
FIG. 1 is a circuit diagram illustrating a conventional nonvolatile memory element including one NMOS transistor and two PMOS transistors. FIG. 2 is a cross-sectional view of the conventional nonvolatile memory element illustrated in FIG. 1. FIG. 3 is a schematic plan view of the conventional nonvolatile memory element.
In FIG. 1, reference numeral 1 denotes a control gate transistor (a PMOS transistor), reference numeral 2 denotes an erase gate transistor (a PMOS transistor), reference numeral 3 denotes a read transistor (an NMOS transistor), reference numeral 4 denotes a control gate, reference numeral 5 denotes an erase gate, reference numeral 6 denotes a drain terminal of the NMOS transistor, reference numeral 7 denotes a source terminal of the NMOS transistor and reference numeral 8 denotes a p-type silicon substrate terminal. Reference numeral 9 denotes a floating gate (FG) connecting the gates of the PMOS transistors 1 and 2 and the gate of the NMOS transistor 3 together.
As illustrated in FIG. 2, the NMOS transistor 3 is formed in a p-type silicon substrate 10 and includes an n-type charge-carrying region and a gate electrode. The PMOS transistors 1 and 2 are provided in n-wells 12 and 11, respectively, in the p-type silicon substrate 10 and each include a p-type charge-carrying region and a gate electrode. The gate electrode of the NMOS transistor 3 is connected to the gates of the PMOS transistors 1 and 2 through the floating gate (FG) 9 and a given voltage is applied to each terminal, thereby performing writing, reading and erasing of carriers on the floating gate (FG) 9.
The conventional nonvolatile memory element using a standard CMOS process has a drawback in which increase of the write speed causes the area occupied by a memory cell to increase and increase of the erase speed is hindered by the limitation of the minimum process size of an erase gate transistor forming the memory cell. Accordingly, in view of cost and physical limitations, demands for application have not been satisfied because of difficulty in increasing the write speed and the erase speed, for example.
A conventional nonvolatile semiconductor memory device using a standard CMOS process has a drawback in which the number of data rewritings is only 1,000 so that reliability equal to that in a flash memory (i.e., 100,000 data rewritings) is not ensured, for example. It is expected that if increase in capacity and more than 1,000 data rewritings are needed in future, the number of data rewritings in a nonvolatile semiconductor memory device becomes an extremely important factor in terms of cost and reliability.
To increase the write speed and the erase speed, a control gate transistor has a capacitance greater than that of a read transistor. This causes the threshold voltage in a charge-0 state (i.e., an ultimate state after reliability deteriorates) to decrease. Accordingly, to utilize advantages of a differential amplifying memory cell exhibiting excellent data retention characteristics, the threshold voltage in an erase state needs to be set extremely low, so that excessive erasure is likely to occur.